Embodiments of the disclosed technology relate to an array substrate of a thin film transistor liquid crystal display (TFT-LCD) and a manufacturing method thereof.
Among liquid crystal displays of various types such as Twisted Nematic (TN) mode, Vertical Alignment (VA) mode and transverse electrical field mode (e.g. In-Plane Switching (IPS) or Fringe Field Switching (FFS)), the transverse electrical field mode has advantages of wide viewing angle, low color aberration, high transmittance and so on, and is more and more widely adopted by respective display panel manufacturers.
FIGS. 1 and 2 show one pixel unit of a transverse electrode filed mode array substrate in which a gate lines 1 and a data lines 2 cross with each other to define a pixel unit. During manufacturing the array substrate, each structure is formed in the following order: a first electrode layer (generally formed by indium tin oxide (ITO), also be referred as 1-ITO) comprising a first electrode 8, as shown in FIG. 2; a gate lines 1, a gate electrode, and a common electrode line; a first insulating layer; source and drain metal electrode layer (comprising a drain electrode 4 and a source electrode 3 of a thin film transistor) and a data line 2; a second insulating layer, which is etched to form a drain contact hole 5; a second electrode layer 2(referred as 2-ITO), which comprises second electrodes 6 and openings 7 in the second electrode layer. In the transverse electrical filed mode TFT LCD array substrate as shown in FIG. 2, since the two ITO layers overlap with each other, i.e. the 2-ITO overlaps with the 1-ITO, the storage capacitance is very large, which results in slow charging for the pixel. This problem is particularly apparent in large-sized high definition products and double frequency driving products.
To solve the above problem, an array substrate as shown in FIG. 3 is proposed in the related arts. In the array substrate, openings 9 are formed in the first electrode layer, and openings 7 are formed in the second electrode layer, so that a plurality of first electrodes 8 and second electrodes 6 spaced apart by these openings are formed in the first and second electrode layer, respectively. The first electrode 8 and the second electrode 6 are staggered so that the first electrode layer and the second electrode layer do not overlap with each other. The array substrate may greatly reduce the storage capacitance. However, since the first electrode layer is a transparent layer, the alignment between the layer and the subsequent layers may be relatively difficult, and the alignment accuracy is relatively poor (generally 3 μm or more). If the overlapping of the two electrode layer occurs due to an alignment error, the storage capacitance will change abruptly, which influences a shift of the charging characteristics of a pixel and causes image defects of the panel. Thus, during actual manufacturing, in order to avoid the overlapping of the two electrode layers caused by the alignment error, the opening of the second electrode layer needs to be wide enough (generally needs to be 10 μm or more), which may result in low transmittance of the pixel in the array substrate.
Another array substrate is proposed in the related arts, as shown in FIG. 4. In the array substrate, openings 9 are formed in the first electrode layer, and openings 7 are formed in the second electrode layer, so that a plurality of first electrodes 8 and second electrodes 6 spaced apart by these openings are formed in the first and second electrode layer, respectively. The first electrode 8 and the second electrode 6 are staggered so that the first electrode layer and the second electrode layer are partially overlapped. This structure may also largely reduce the storage capacitance. In such an array substrate, the opening width of the first electrode layer is smaller than the width of each second electrode in the second electrode layer. Generally, in the transverse electrical field mode TFT-LCD array substrate, the electrode width of the second electrode layer is only 3˜4 μm. Thus, the opening width of the first electrode layer is required to be even smaller, only 2˜3 μm. It is very difficult to accomplish such an opening width under the conventional process conditions. Similarly, such an array substrate also has the problem that the poor alignment accuracy will influence the change of the storage capacitance, thus the process property is poor. In order to avoid the influence on the storage capacitance by the alignment error, the electrode width of the second electrode layer needs to be greatly increased, which will cause large reduction in the transmittance of the pixel.